1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating an MOS device.
2. Discussion of the Related Art
In general, with a worldwide trend toward high integration, high density, and high performance that quadruples over approximately every three-year period, miniaturization of semiconductor devices has been rapid. However, the miniaturization of the semiconductor devices have resulted in a strengthened field intensity which has deteriorated the characteristics of the semiconductor devices. The strengthened field intensity has caused other problems as well.
As the width of a gate becomes narrow, a field collection occurs in a drain region that is high so as to affect the characteristics of the semiconductor device. To reduce such a field, a low-concentration doping with a slow profile has to be performed between the drain region and a channel. That is, doping is heavily performed in the source and drain regions, but lightly performed in a region adjacent to the channel to form a lightly doped drain (LDD) structure.
A dopant such as phosphorus (P) or arsenic (As) has been used when forming the LDD structure of NMOS. For a wide doping profile using P, a high breakdown voltage BV of 8 V or more occurs in a device having a long channel with a length of 0.5 um or more. When using As, a breakdown voltage BV of 6 V or more occurs in a device having a short channel with a length of 0.3 um or more. However, this has brought another problem. For example, the reliability of the device deteriorates from implanting the same ion into all the devices having separate channel characteristics, respectively. In other words, when using P as a dopant, minimization of the channel cannot be achieved but a high enough breakdown voltage can be achieved. When using As as a dopant, a high breakdown voltage BV cannot be achieved but characteristics of a short channel length can be achieved.
A conventional method of fabricating a semiconductor device will now be described with reference to the appended drawings.
FIGS. 1a to 1d are sectional views showing fabricating processes of a conventional MOS device.
As shown in FIG. 1a, a first insulating film 2, a poly-crystal silicon and a second insulating film 4 are sequentially deposited on an N type semiconductor substrate 1. Then, the first insulating film 2, the poly-crystal silicon and the second insulating film 4 are selectively removed by photolithography and etching process to form a plurality of gate electrodes 3 having a separate channel length, respectively.
As shown in FIG. 1b, low-concentration impurity ions such as P or As are implanted into the entire surface of the substrate 1 including the gate electrodes 3 to form an LDD region 5 on the substrate 1 at both sides of the electrodes 3. As shown in FIG. 1c, a third insulating film is formed on the entire surface of the substrate 1 including the gate electrodes 3. Gate sidewall spacers 6 are formed at both sides of the gate electrodes 3 by an anisotropic etching. As shown in FIG. 1d, high-concentration impurity ions are implanted into the entire surface of the substrate 1 including the gate electrodes 3 to form source and drain regions 7 in the substrate 1 at both sides of the gate sidewall spacers 6.
However, the conventional method of fabricating a semiconductor device as discussed above has several problems.
First, by implanting the same LDD ions such as P or As into all the devices having separate channel characteristics respectively, the reliability of the device deteriorates since a voltage applied to a circuit varies depending on the respective device. Thus, using P as a dopant is suitable for a high voltage device since the breakdown voltage BV is high enough. However, it is not suitable for a low voltage device having a minimum channel length.
On the other hand, using As as a dopant is suitable for a low voltage device having characteristics of a short channel length. However, it is not suitable for a high voltage device having a high breakdown voltage.